1. Field of the Invention
The present invention generally relates to semiconductor chip fabrication, and more particularly to a method for generating an optical proximity correction (OPC) model for printing a circuit pattern on a photoresist layer of a semiconductor wafer. The invention is also an optical lithography system which generates an OPC model of this type.
2. Description of the Related Art
Model-based and hybrid rules/model-based optical proximity correction schemes are becoming the standard in the industry. In many situations, and especially when applying assist features, it makes the most sense to use a rules-based approach to apply some corrections followed by a model-based correction to clean up any problem spots. In order for this scheme to work, the rules and model must be compatible, so that the model-based correction does not find errors with the desired rules-based corrections.
OPC models are typically broken into two sections. One section describes the aerial image that is expected from a given wafer pattern and the other section describes the effects of the mask making and lithography/etch processes. OPC models of this type are calibrated by measuring the dimensions of known test structures exposed on a wafer. The aerial images of the test structures are then computed and the difference between these and the measured structures is used to determine the process model.
More sophisticated methods have been proposed to generate rules tables for a rules-based approach to optical proximity correction. Although not widely used, it has been shown that a process window analysis can be used to determine an optimum rules table. See Mansfield et al., Lithographic Comparison of Assist Feature Design Strategies, Proc. SPIE 4000, (2000). The benefit of this method is that it can be extended to account for expected mask and stepper lens errors, as well as process variations.
In view of the foregoing considerations, it is clear that a need exists for a method of generating an OPC model that is not only compatible with a sophisticated rules generation method, but also is able to take advantage of this additional sophistication.
It is a first object of the present invention to provide a method for generating an improved OPC model for correcting errors in the image of an integrated circuit formed on a resist layer of a semiconductor wafer.
It is another object of the present invention to achieve the first object by, first, generating a set of correction rules and then generating the OPC model based on the set of correction rules, which is a different and more effective approach than the conventionally taken which conversely to the invention first generates a model and then generates a set of correction rules based on that model. One advantage of the approach taken by the invention derives from the use of sophisticated rules generation methods which determine correction rules that account for variations in mask and wafer processes. Conventional methods used to generate OPC models do not account for such process variations.
It is another object of the present invention to provide a method for is generating an OPC model which is not only compatible with a sophisticated rules generation method but also is able to take advantage of this additional sophistication.
It is another object of the present invention to provide a method for generating an OPC model which is based on optimizing the process window to print features of interest.
It is another object of the present invention to provide a method for generating an OPC model where the process window includes the effects of process variations, mask errors, and errors in the exposure tools used.
It is another object of the present invention to generate an OPC model based on OPC rules.
It is another object of the present invention to use a process window analysis to generate rules to create an OPC model.
It is another object of the present invention to use designed lines at a reference spacing to create resist target dimensions from which the OPC model is generated.
It is another object of the present invention to create an input table with fixed resist sizes and variable line sizes to calibrate an OPC model.
The foregoing and other objects of the invention are achieved by a method which generates an optical proximity correction (OPC) model in accordance with steps that include generating a set of correction rules for a wafer design containing a multitude of lines separated from each other by various spacings, determining a set of corrections that need to be made over a range of sizes and spaces of said lines based on the set of correction rules, and then creating an optical proximity correction model for correcting the wafer design based on the set of corrections. This methodology works equally well for photomask designs that either do or do not utilize sub-resolution assist features. Preferably, the correction rules are generated using a process window analysis, although a line-width analysis may also be used.